1. Field Of The Invention
The present invention relates to integrated circuits and electronic circuits within integrated circuits used as sense amplifiers which find application in memory circuits such as random access memory, programmable read-only memory, and readonly memory to detect the presence or absence of an active memory signal. More particularly, the present invention is a high-speed static differential sense amplifier.
2. The Prior Art
The conventional voltage sensing static differential sense amplifier contains two data paths. Each data path has four branches divided into two stages. The two data paths are used to maintain a differential signal through the amplification chain. Maintaining a differential signal improves the noise margin by rejecting the common mode noise. Each stage uses two branches to double their effective input voltage, and thereby more than double their single-ended output voltage. To maintain a differential signal, a complimentary stage is necessary to produce a matching signal with the opposite polarity. Such an amplifier is shown in FIG. 1.
The conventional differential sense amplifier is relatively slow due to the large number of branches required to maintain a differential signal. For example, in the conventional design there are four branch delays between the input and the output. Some dynamic sense amplifiers have only two branch delays. Therefore, the conventional static differential sense amplifier design is inherently slower then the dynamic differential sense amplifier.
The conventional static differential sense amplifier also uses a large amount of current. There are eight branches consuming eight separate bias currents. If this sense amplifier were used in an eight output product there would be 64 separate branches consuming DC current. For products having multiple outputs, the output drive current of each branch must be sacrificed to control the current consumption which usually makes the sense amplifier slower since there is less current available to drive the load. One solution to this drive problem is to add another logic stage to regain the lost drive. However, adding such a stage only adds another delay and makes the product even slower.